# 应用示例

## 内存到内存传输
```c
    GX_DMA_AHB_CH_CONFIG dma_config = {0};

	int channel = gx_dma_select_channel();

	if(channel == -1)
		return -1;

	dma_config.trans_width  = GX_DMA_AHB_TRANS_WIDTH_8;
	dma_config.flow_ctrl = GX_DMA_AHB_TT_FC_MEM_TO_MEM_DMAC;

	dma_config.src_msize  = GX_DMA_AHB_BURST_TRANS_LEN_8;
	dma_config.src_addr_update	= GX_DMA_AHB_CH_CTL_L_INC;
	dma_config.src_master_select  = GX_DMA_AHB_MASTER_3;

	dma_config.dst_addr_update	= GX_DMA_AHB_CH_CTL_L_INC;
	dma_config.dst_msize  = GX_DMA_AHB_BURST_TRANS_LEN_8;
	dma_config.dst_master_select  = GX_DMA_AHB_MASTER_3;

	if(gx_dma_xfer_poll(dst, (void *)src, count, channel, &dma_config) != 0)
		return -1;
```

## 读外设数据
```c
    GX_DMA_AHB_CH_CONFIG dma_config = {0};
    int dma_channel;

    dma_channel = gx_dma_select_channel();
    if (dma_channel < 0) {
        return -1;
    }

    dma_config.trans_width = GX_DMA_AHB_TRANS_WIDTH_8;

    /* dma source config */
    dma_config.src_addr_update = GX_DMA_AHB_CH_CTL_L_NOINC;
    dma_config.src_hs_select = GX_DMA_AHB_HS_SEL_HW;
    dma_config.src_master_select = GX_DMA_AHB_MASTER_2;
    dma_config.src_msize = GX_DMA_AHB_BURST_TRANS_LEN_8;
    dma_config.src_hs_per = DMA_HS_PRE_FLASH_SPI_RX;

    /* dma destination config */
    dma_config.dst_addr_update = GX_DMA_AHB_CH_CTL_L_INC;
    dma_config.dst_hs_select = GX_DMA_AHB_HS_SEL_HW;
    dma_config.dst_master_select = GX_DMA_AHB_MASTER_3;
    dma_config.dst_msize = GX_DMA_AHB_BURST_TRANS_LEN_32;
    dma_config.dst_hs_per = 0;

    dma_config.flow_ctrl = GX_DMA_AHB_TT_FC_PER_TO_MEM_DMAC;
//	gx_dcache_invalid_range((unsigned int *)data, len);
    gx_dma_xfer((void *)data, (void *)DISP_SPIM_RXDR_LE,len, dma_channel, &dma_config);

    gx_dma_wait_complete(dma_channel);
```

## 写外设数据
```c
    GX_DMA_AHB_CH_CONFIG dma_config = {0};
    int dma_channel;

    dma_channel = gx_dma_select_channel();
    if (dma_channel < 0) {
        return -1;
    }

    dma_config.trans_width = GX_DMA_AHB_TRANS_WIDTH_8;
    /* dma source config */
    dma_config.src_addr_update = GX_DMA_AHB_CH_CTL_L_INC;
    dma_config.src_hs_select = GX_DMA_AHB_HS_SEL_HW;
    dma_config.src_master_select = GX_DMA_AHB_MASTER_3;
    dma_config.src_msize = GX_DMA_AHB_BURST_TRANS_LEN_32;
    dma_config.src_hs_per = 0;

    /* dma destination config */
    dma_config.dst_addr_update = GX_DMA_AHB_CH_CTL_L_NOINC;
    dma_config.dst_hs_select = GX_DMA_AHB_HS_SEL_HW;
    dma_config.dst_master_select = GX_DMA_AHB_MASTER_2;
    dma_config.dst_msize = GX_DMA_AHB_BURST_TRANS_LEN_8;
    dma_config.dst_hs_per = DMA_HS_PRE_FLASH_SPI_TX;

    dma_config.flow_ctrl = GX_DMA_AHB_TT_FC_MEM_TO_PER_DMAC;

    //	gx_dcache_clean_range((unsigned int *)data, len);
    gx_dma_xfer((void *)DISP_SPIM_TXDR_LE, (void *)data,len, dma_channel, &dma_config);
    gx_dma_wait_complete(dma_channel);
```